In general, EEPROM cells in a semiconductor device exhibit non-volatile properties capable of retaining data stored therein even when the supply of power is interrupted. Also, each of the EEPROM cells has a floating gate for storing the data. The floating gate is electrically isolated and stores electric charges therein. The data stored in an EEPROM cell may be classified into logic “1” and logic “0” data depending on an amount of electric charges stored in the floating gate.
Recently, flash ROM is based on such EEPROM. With the conventional EEPROM it is difficult to attain a high coupling ratio in proportion to an increase in its density, and thus requires high operating voltage for programming/erasing and needs a sophisticated electronic circuit using a time division procedure which is temporally precise and an intermediate verification algorithm for stable operation.
FIG. 1 is a cross-sectional view showing a conventional EEPROM.
With reference to FIG. 1, the conventional EEPROM 100 includes two layers of polysilicon (poly-Si) manufactured at high yield through a simple process. The EEPROM 100 uses a high voltage of about 18V during programming/erasing and thus a solution for preventing excessive current generation during programming/erasing is needed, such as additional current limitation, terminal floating and the like. However, owing to sophisticated peripheral circuits and supply of high operating voltage, the manufacturing process of an EEPROM becomes simple and an area thereof gets reduced, whereby the EEPROM is widely employed in large-capacity chips.
As mentioned above, conventional EEPROM used in a small-scale for embedded system-on-chip (SoC) applications such as a smart card or a typical electronic apparatus should include an additional sophisticated electronic circuit to ensure a high operating voltage and stable operation thereof, but such an additional electronic circuit is complicated to be implemented and adopted.